This invention relates to a central processing unit (CPU) for an electronic data processing system and, more particularly to a CPU which provides programmable optional autoincrementing of memory pointer registers without requiring that the autoincrementing condition of each memory pointer register be specified by the operation code (op-code) of an instruction.
Autoincrementing is the process by which certain registers containing memory location addresses are automatically incremented when referenced in an instruction. Incrementation involves the addition (or subtraction) of a specified quantity to the address contained in a certain register to form a new address which is associated with a memory location containing the next operand to be used by the CPU. Autoincrementing is useful in examining the contents of tables or arrays of memory locations and enables the contents of memory pointer registers to be advanced to other locations in such tables or arrays without the need for separate instructions for modifying those contents.
The op-code of an instruction is a group of binary digits (bits) that define a processor operation such as ADD, SUBTRACT, COMPLEMENT, etc. The set of processor operations formulated for a CPU depends on the processing it is intended to carry out. The total number of distinct operations which can be performed by the CPU determines its set of processor operations.
The number of bits which form the op-code (op-code field) is a function of the number of operations in the set. At least N bits are necessary to define 2.sup.N or less distinct operations. The CPU designer assigns a different bit combination (i.e., op-code) to each operation. The controller section of the CPU detects the bit combination at the proper time in a sequence and produces proper command signals to required destinations in the CPU to execute the specified operation.
In addition to specifying a processor operation, an instruction will normally also carry other information such as means for determining the address(es) of memory locations where operand(s) to be used in the processor operations are stored. In many instruction formats, the number of bits required for the operand address(es) (address field) occupy most of the bit positions available in the instruction leaving only a limited number of bits to be allocated for the op-code field. When a CPU designer finds the bits allocated to the op-code field insufficient for a given set of processor operations he has, heretofore, had the choice of either accepting a smaller set of processor operations or lengthening the instruction.
Prior art techniques for permitting program control of autoincrementing have been to use a designated bit in the op-code or the memory address mode code to specify the autoincrementing condition of each memory pointer register. Where the op-code or the memory address mode code length is insufficient to define new codes, additional bits must be added. For example, if two memory pointer registers are to have the optional autoincrementing feature, two bits in the op-code would have to be reserved to specify the autoincrementing condition of the two registers. However, adding bits to the op-code or the memory address mode code has the effect of making the instructions longer.
Long instructions are disadvantageous in small data processing systems where the memory capacity for storing instructions is limited. In addition, small systems have limited word sizes as well (as small as 4 bits in some systems where the CPU is in the form of a microprocessor), and a long instruction has the added disadvantage of requiring many memory references for retrieval and, thus, of slowing down CPU operation. However, from the standpoint of versatility, programming convenience, and operating efficiency, it is desirable to have optional programmable autoincrementing. Therefore, a problem in designing a CPU for small data processing systems is that of being able to define optional, programmable autoincrementing while minimizing instruction length.